Epitaxial layers of single crystalline silicon (Si) films grown over silicon substrate are widely used in semiconductor manufacturing. FIG. 1 shows a single crystal substrate 10, with a grown epitaxial layer 20 (epi layer) and an interfacial surface 30 (interface) such as discussed in this application. In some applications such as silicon on-insulator, substrate 10 need not be single crystalline. Layer 20 can in turn be comprised of a plurality of epitaxial layers and correspondingly a plurality of interfaces 30 can be present. Layer 20, as grown, is single crystalline and has the same crystal orientation as substrate 10. Therefore, layer 20 can be used to form various parts of a semiconductor device that requires the semiconducting single crystal behavior for device operation. Further, the ability to dope the epi layers with selected impurities at different concentrations during film growth simplifies device manufacturing processes and provides the ability to tailor the device structure. In addition, in the absence of epitaxy film layering capability, the choice of a substrate for a given device may be restricted. For example, a "latch-up" problem in high frequency circuits using Complementary Metal Oxide Semiconductor (CMOS) devices can be minimized or avoided by using a highly doped (or conductive) substrate. In the absence of this requirement, CMOS devices will be preferably built on a low doped, highly resistive substrates. Epitaxy layering in the manufacturing of CMOS devices is very valuable.
In silicon epitaxy, a thin single crystalline film (or layer) of Si is grown on a bulk single crystal Si substrate. In CMOS devices, usually a single layer of epitaxial film is used, in which the different parts of a Field Effect Transistor (FET) such as source, drain, channel are formed. In Bipolar devices, several epitaxial layers are typically formed, each one being used to form different parts of a bipolar transistor such as sub-collector, collector and base. In particular, the thickness of the sub-collector layer is kept large to minimize the resistivity of the sub-collector region. A second epi layer is deposited over a first epi layer and is used for defining the collector and base regions. Accordingly, the thickness of epitaxial films used in Bipolar devices is of the order of 6-10 microns, significantly higher than that required for CMOS devices.
The epitaxy process is usually carried out in a temperature range of 850.degree. C. to 1200.degree. C. and typical process conditions can be readily found in the literature (Runyan, in Silicon Devices, eds., Haberecht and Kern, 1969, The Electrochemical Society, pp. 169-187). The nucleation and growth of the epi layer 20, which has the same orientation as the Si substrate 10 on which it is grown, usually results in many associated point and line defects at the interface 30 as a result of the growth process. The generation of these defects is primarily to accommodate the lattice mismatch between the atomic ordering and spacing of the substrate underneath and the epi film growing on top of it. This mismatch among other things is strongly influenced by the difference in conductivity of the substrate and epitaxial layer. FIG. 2 shows a plot of lattice constant of a Si single crystal containing different dopant concentrations (Sugita and Tamura, Journal of Applied Physics, 40(8), 1969, pp. 389-394). The misfit grows progressively worse with increase in dopant concentration and difference in dopant concentration between substrate and the grown film. For example, when the substrate is heavily doped, an intrinsic or low doped layer will result in a larger misfit and larger mismatch strain than when the doping levels are similar. One type of common defect, called a misfit dislocation, is generated at the bulk Si--epi Si interface 30 of FIG. 1, as a way to accommodate and relieve this strain. Misfit dislocations are a source of dislocations in the epi films which can affect the device yield.
Another issue of importance in growing doped epitaxial film over doped substrates is the phenomenon of autodoping. Autodoping is the unwanted transfer of dopants present in the substrate into the grown epi layer, through the vapor phase, during the high temperature epitaxial growth process. Autodoping can occur between wafers and between regions of the wafer. For example, the backside of a highly doped substrate can contribute excess dopants to the epitaxy ambient that alters the concentration or kind of dopants that are being grown into the epi film. This autodoping is usually minimized or avoided by having a masking layer (such as silicon dioxide) to cover substrate surfaces, and further optimizing epitaxial process conditions such as deposition temperature and pressure. In most cases, where a blanket epi layer is desired on a highly conductive substrate, the backside of the wafer is selectively coated by using a low temperature process such as atmospheric chemical vapor deposition (APCVD), plasma enhanced chemical vapor deposition (PECVD) or low temperature oxide (LTO). These films usually have a compressive film stress similar to thermal oxide.
Defects such as dislocations are undesirable in single crystal Si substrates and epi Si layers, especially when they are present in regions where devices are to be formed. A dislocation or a cluster of dislocations attract metallic and ionic impurities and can provide an unwanted electrical conductive path between different regions of the semiconductor device. For example, a dislocation extending from a collector to an emitter region can cause leakage at low voltages in a Bipolar device. This is shown in FIG. 6, wherein a dislocation 290 extends across an emitter region 280 and a sub-collector region 220 thereby causing unacceptable emitter to collector current leakage. This type of leakage and associated yield losses will be referred to as pipe losses in this application. Pipe limited yield is an important measure in semiconductor manufacturing process and is used in the same connotation as pipe losses. Many precautions are taken in semiconductor manufacturing to reduce pipe losses.
The occurrence of misfit dislocations in epitaxy layer deposition has been widely studied. FIG. 3 (Kikuchi et al., Appl. Phys. Lett. 54(5), Jan. 1989, p. 464, FIG. 2) shows both theoretical calculation on when misfit dislocations can occur and also the observed occurrence of misfit dislocations for a 4 inch (100) oriented substrate. The experimental data is gathered using three different levels of boron (B) doped substrate and epi layers having a thickness in the range of 1-10 microns, and resistivities in the range of 0.7-1.3 ohm-cm. Both the experimental and theoretical curves show the trend that when the substrate conductivity is increased, the critical thickness of an epitaxy layer to avoid misfit dislocation generation decreases sharply. Heretofore, an application desiring a high conductivity substrate would be limited to a thinner epitaxial layer in order to avoid misfit dislocation generation. The difference between calculated and observed curves suggest that the theory probably predicts sufficient conditions for misfit dislocation occurrence and the experimentally observed data suggest that other factors play a role to mitigate the mismatch effect. However, the experimental curve and the theoretical curve clearly follows the same trend that when there is a large mismatch in conductivity between the substrate and the epi layer, the epi layer thickness need to be kept small to avoid generation of misfit dislocations.
CMOS devices usually can be designed with an epi layer of the order of less than 5 microns, as the FET is a surface device and the source, channel and drain regions are shallow with respect to the surface of the epi layer. However Bipolar devices require thicker epi layers. In devices such as BiCMOS, the combined requirements of a thicker epi film for Bipolar devices and a high conductive substrate for CMOS devices, lead to unacceptable pipe losses. Accordingly, there is a clear need for methods and processes that allow decoupling of substrate conductivity and the thickness of epitaxial layers without the concern of pipe losses.
It is therefore a feature of the present invention to provide a method to provide epitaxially grown semiconductor layers usable thickness with low resistive substrates with minimal dislocations.
It is a feature of the present invention to provide a process that improves pipe limited yield in processes requiring a thick epitaxy layer such as the formation of BiCMOS devices.
It is a further feature of the present invention that such a process be compatible with conventional semiconductor manufacturing processes.
It is yet another feature of the present invention that such a process be relatively simple and inexpensive.